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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>H:\nestang\nestang-25k\src\MicroCode.v<br>
H:\nestang\nestang-25k\src\apu.v<br>
H:\nestang\nestang-25k\src\autofire.v<br>
H:\nestang\nestang-25k\src\compat.v<br>
H:\nestang\nestang-25k\src\config.sv<br>
H:\nestang\nestang-25k\src\cpu.v<br>
H:\nestang\nestang-25k\src\dualshock_controller.v<br>
H:\nestang\nestang-25k\src\game_loader.v<br>
H:\nestang\nestang-25k\src\gowin_clkdiv\gowin_clkdiv.v<br>
H:\nestang\nestang-25k\src\gowin_pll\gowin_pll.v<br>
H:\nestang\nestang-25k\src\gowin_rpll_usb.v<br>
H:\nestang\nestang-25k\src\hdmi\gowin_pll\gowin_pll_hdmi.v<br>
H:\nestang\nestang-25k\src\hdmi2\audio_clock_regeneration_packet.sv<br>
H:\nestang\nestang-25k\src\hdmi2\audio_info_frame.sv<br>
H:\nestang\nestang-25k\src\hdmi2\audio_sample_packet.sv<br>
H:\nestang\nestang-25k\src\hdmi2\auxiliary_video_information_info_frame.sv<br>
H:\nestang\nestang-25k\src\hdmi2\hdmi.sv<br>
H:\nestang\nestang-25k\src\hdmi2\packet_assembler.sv<br>
H:\nestang\nestang-25k\src\hdmi2\packet_picker.sv<br>
H:\nestang\nestang-25k\src\hdmi2\serializer.sv<br>
H:\nestang\nestang-25k\src\hdmi2\source_product_description_info_frame.sv<br>
H:\nestang\nestang-25k\src\hdmi2\tmds_channel.sv<br>
H:\nestang\nestang-25k\src\hw_sound.v<br>
H:\nestang\nestang-25k\src\hw_uart.v<br>
H:\nestang\nestang-25k\src\memory_controller.v<br>
H:\nestang\nestang-25k\src\mmu.v<br>
H:\nestang\nestang-25k\src\nes.v<br>
H:\nestang\nestang-25k\src\nes2hdmi.sv<br>
H:\nestang\nestang-25k\src\nes_tang25k.v<br>
H:\nestang\nestang-25k\src\ppu.v<br>
H:\nestang\nestang-25k\src\sd_file_list_reader.v<br>
H:\nestang\nestang-25k\src\sd_loader.v<br>
H:\nestang\nestang-25k\src\sd_reader.sv<br>
H:\nestang\nestang-25k\src\sdcmd_ctrl.sv<br>
H:\nestang\nestang-25k\src\sdram.v<br>
H:\nestang\nestang-25k\src\uart_tx_V2.v<br>
H:\nestang\nestang-25k\src\usb_hid_host.v<br>
H:\nestang\nestang-25k\src\usb_hid_host_rom.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Oct 30 14:57:29 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>NES_Tang25k</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 427.742MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 427.742MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.213s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 427.742MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.454s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.793s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 1m 8s, Elapsed time = 0h 1m 9s, Peak memory usage = 427.742MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 427.742MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 427.742MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 1m 24s, Elapsed time = 0h 1m 25s, Peak memory usage = 427.742MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>72</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>68</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>7</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>34</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIOBUF</td>
<td>21</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspELVDS_OBUF</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>4927</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>95</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>3579</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>19</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>1234</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>8522</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>910</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>2687</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>4925</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>1066</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>1066</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>14</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16S4</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16SDP4</td>
<td>6</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>65</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>65</td>
</tr>
<tr>
<td class="label"><b>IOLOGIC </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOSER10</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>DSP </b></td>
<td></td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULTALU27X18</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULT12X12</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULT27X36</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULTADDALU12X12</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>36</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>27</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsppROM</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsppROMX9</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspCLKDIV</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspPLLA</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>9737(8587 LUT, 1066 ALU, 14 RAM16) / 23040</td>
<td>43%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>4927 / 23280</td>
<td>22%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 23280</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>4927 / 23280</td>
<td>22%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>36 / 56</td>
<td>65%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>sys_clk_ibuf/I </td>
</tr>
<tr>
<td>u_hdmi/clk_audio_5</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>u_hdmi/clk_audio_s0/Q </td>
</tr>
<tr>
<td>controller/pls/W_scan_seq_pls_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q </td>
</tr>
<tr>
<td>sclk_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>sclk_s1/Q </td>
</tr>
<tr>
<td>controller/pls/W_TXSET_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller/pls/W_TXSET_s/F </td>
</tr>
<tr>
<td>controller/txd/n4_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller/txd/n4_s2/O </td>
</tr>
<tr>
<td>controller/pls/joystick_clk_d_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller/pls/joystick_clk_d_s/F </td>
</tr>
<tr>
<td>controller/n50_15</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller/n50_s1/F </td>
</tr>
<tr>
<td>controller2/pls/W_scan_seq_pls_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller2/pls/O_SCAN_SEQ_PLS_s0/Q </td>
</tr>
<tr>
<td>controller2/pls/W_TXSET_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller2/pls/W_TXSET_s/F </td>
</tr>
<tr>
<td>controller2/pls/joystick_clk2_d_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller2/pls/joystick_clk2_d_s/F </td>
</tr>
<tr>
<td>controller2/n50_15</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller2/n50_s1/F </td>
</tr>
<tr>
<td>controller/n50_16</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller/n50_s2/O </td>
</tr>
<tr>
<td>controller2/n50_16</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>controller2/n50_s2/O </td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Generated</td>
<td>83.333</td>
<td>12.0</td>
<td>0.000</td>
<td>41.667</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0 </td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT1.default_gen_clk</td>
<td>Generated</td>
<td>40.000</td>
<td>25.0</td>
<td>0.000</td>
<td>20.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>pll_clk/PLLA_inst/CLKOUT1 </td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
<td>Generated</td>
<td>2.667</td>
<td>375.0</td>
<td>0.000</td>
<td>1.333</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2 </td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
<td>Generated</td>
<td>40.000</td>
<td>25.0</td>
<td>0.000</td>
<td>20.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3 </td>
</tr>
<tr>
<td>clk_div/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>13.333</td>
<td>75.0</td>
<td>0.000</td>
<td>6.667</td>
<td>pll_clk/PLLA_inst/CLKOUT2</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
<td>clk_div/clkdiv_inst/CLKOUT </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>sys_clk</td>
<td>50.0(MHz)</td>
<td>153.8(MHz)</td>
<td>10</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>u_hdmi/clk_audio_5</td>
<td>100.0(MHz)</td>
<td>421.9(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>sclk_6</td>
<td>100.0(MHz)</td>
<td>361.7(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>controller/pls/W_TXSET_2</td>
<td>100.0(MHz)</td>
<td>253.9(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>controller/txd/n4_6</td>
<td>100.0(MHz)</td>
<td>747.7(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>6</td>
<td>controller/pls/joystick_clk_d_2</td>
<td>100.0(MHz)</td>
<td>1577.9(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>7</td>
<td>controller2/pls/W_TXSET_2</td>
<td>100.0(MHz)</td>
<td>259.5(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>8</td>
<td>controller2/pls/joystick_clk2_d_2</td>
<td>100.0(MHz)</td>
<td>1577.9(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>9</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>12.0(MHz)</td>
<td>168.4(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
<tr>
<td>10</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
<td>25.0(MHz)</td>
<td>38.8(MHz)</td>
<td>38</td>
<td>TOP</td>
</tr>
<tr>
<td>11</td>
<td>clk_div/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>75.0(MHz)</td>
<td>76.3(MHz)</td>
<td>20</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.565</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>921.486</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>920.920</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/game_d_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.498</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>917.686</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/CLK</td>
</tr>
<tr>
<td>918.068</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/Q</td>
</tr>
<tr>
<td>918.256</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n269_s1/I0</td>
</tr>
<tr>
<td>918.782</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>n269_s1/F</td>
</tr>
<tr>
<td>918.969</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s1/I3</td>
</tr>
<tr>
<td>919.232</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>sd_loader/n3112_s1/F</td>
</tr>
<tr>
<td>919.419</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s0/I2</td>
</tr>
<tr>
<td>919.881</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>sd_loader/n3112_s0/F</td>
</tr>
<tr>
<td>920.068</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2538_s2/I1</td>
</tr>
<tr>
<td>920.584</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>920.772</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2538_s1/I0</td>
</tr>
<tr>
<td>921.298</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2538_s1/F</td>
</tr>
<tr>
<td>921.486</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_6_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>920.831</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>921.019</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_6_s0/CLK</td>
</tr>
<tr>
<td>920.984</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>sd_loader/debounce_6_s0</td>
</tr>
<tr>
<td>920.920</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>sd_loader/debounce_6_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.293, 60.329%; route: 1.125, 29.605%; tC2Q: 0.382, 10.066%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.565</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>921.486</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>920.920</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/game_d_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.498</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>917.686</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/CLK</td>
</tr>
<tr>
<td>918.068</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/Q</td>
</tr>
<tr>
<td>918.256</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n269_s1/I0</td>
</tr>
<tr>
<td>918.782</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>n269_s1/F</td>
</tr>
<tr>
<td>918.969</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s1/I3</td>
</tr>
<tr>
<td>919.232</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>sd_loader/n3112_s1/F</td>
</tr>
<tr>
<td>919.419</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s0/I2</td>
</tr>
<tr>
<td>919.881</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>sd_loader/n3112_s0/F</td>
</tr>
<tr>
<td>920.068</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2538_s2/I1</td>
</tr>
<tr>
<td>920.584</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>920.772</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2536_s1/I0</td>
</tr>
<tr>
<td>921.298</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2536_s1/F</td>
</tr>
<tr>
<td>921.486</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_8_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>920.831</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>921.019</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_8_s0/CLK</td>
</tr>
<tr>
<td>920.984</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>sd_loader/debounce_8_s0</td>
</tr>
<tr>
<td>920.920</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>sd_loader/debounce_8_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.293, 60.329%; route: 1.125, 29.605%; tC2Q: 0.382, 10.066%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.565</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>921.486</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>920.920</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/game_d_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.498</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>917.686</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/CLK</td>
</tr>
<tr>
<td>918.068</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/Q</td>
</tr>
<tr>
<td>918.256</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n269_s1/I0</td>
</tr>
<tr>
<td>918.782</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>n269_s1/F</td>
</tr>
<tr>
<td>918.969</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s1/I3</td>
</tr>
<tr>
<td>919.232</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>sd_loader/n3112_s1/F</td>
</tr>
<tr>
<td>919.419</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s0/I2</td>
</tr>
<tr>
<td>919.881</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>sd_loader/n3112_s0/F</td>
</tr>
<tr>
<td>920.068</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2538_s2/I1</td>
</tr>
<tr>
<td>920.584</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>920.772</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2535_s1/I0</td>
</tr>
<tr>
<td>921.298</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2535_s1/F</td>
</tr>
<tr>
<td>921.486</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_9_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>920.831</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>921.019</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_9_s0/CLK</td>
</tr>
<tr>
<td>920.984</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>sd_loader/debounce_9_s0</td>
</tr>
<tr>
<td>920.920</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>sd_loader/debounce_9_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.293, 60.329%; route: 1.125, 29.605%; tC2Q: 0.382, 10.066%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.565</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>921.486</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>920.920</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/game_d_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.498</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>917.686</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/CLK</td>
</tr>
<tr>
<td>918.068</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/Q</td>
</tr>
<tr>
<td>918.256</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n269_s1/I0</td>
</tr>
<tr>
<td>918.782</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>n269_s1/F</td>
</tr>
<tr>
<td>918.969</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s1/I3</td>
</tr>
<tr>
<td>919.232</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>sd_loader/n3112_s1/F</td>
</tr>
<tr>
<td>919.419</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s0/I2</td>
</tr>
<tr>
<td>919.881</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>sd_loader/n3112_s0/F</td>
</tr>
<tr>
<td>920.068</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2538_s2/I1</td>
</tr>
<tr>
<td>920.584</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>920.772</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2533_s1/I0</td>
</tr>
<tr>
<td>921.298</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2533_s1/F</td>
</tr>
<tr>
<td>921.486</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_11_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>920.831</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>921.019</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_11_s0/CLK</td>
</tr>
<tr>
<td>920.984</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>sd_loader/debounce_11_s0</td>
</tr>
<tr>
<td>920.920</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>sd_loader/debounce_11_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.293, 60.329%; route: 1.125, 29.605%; tC2Q: 0.382, 10.066%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.565</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>921.486</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>920.920</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/game_d_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.498</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>917.686</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/CLK</td>
</tr>
<tr>
<td>918.068</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>usb_controller2/game_d_s0/Q</td>
</tr>
<tr>
<td>918.256</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n269_s1/I0</td>
</tr>
<tr>
<td>918.782</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>n269_s1/F</td>
</tr>
<tr>
<td>918.969</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s1/I3</td>
</tr>
<tr>
<td>919.232</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>sd_loader/n3112_s1/F</td>
</tr>
<tr>
<td>919.419</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n3112_s0/I2</td>
</tr>
<tr>
<td>919.881</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>sd_loader/n3112_s0/F</td>
</tr>
<tr>
<td>920.068</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2538_s2/I1</td>
</tr>
<tr>
<td>920.584</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>920.772</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2530_s1/I0</td>
</tr>
<tr>
<td>921.298</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/n2530_s1/F</td>
</tr>
<tr>
<td>921.486</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_14_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>920.831</td>
<td>0.831</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>921.019</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>sd_loader/debounce_14_s0/CLK</td>
</tr>
<tr>
<td>920.984</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>sd_loader/debounce_14_s0</td>
</tr>
<tr>
<td>920.920</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>sd_loader/debounce_14_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.293, 60.329%; route: 1.125, 29.605%; tC2Q: 0.382, 10.066%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.188, 100.000%</td></tr>
</table>
<br/>
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